1、BTS?2?BTS2003?4?Version 1.0?!?#$?%&()*+?,-./?0?%123?450?%673?0?%123?89:;0?%12Timing Analyzer3?0?%673?-Static Timing Analysis(STA)?AB?&?89CD45?EFG?H?IJKLMNOPQ?R?FG?STU?V?LMTWXY?Z?_abcdefg45?Mhi?45jklm?nopqrs?tuJ?vw89xygzbs&AB?|?100%?45?/?0timing closure3?-Static Timing Analysis(STA)?89?z?Jvw?+?/?/?(?
2、a?/?)?“?Ru?Rfi“rs?R?fl?HH?lmY?C?89”?EDC?.?r?a?FG?IMT45.?.B?R?f?jk?-Static Timing Analysis(STA)?Synopsys?PrimeTime?Mentor Graphics?SST Velocity?N?IC?&Primetime?k?89&?Innoveda?Blast89?NFPGA?s?s?&?FPGA?89?&FPGA?JIC?&?ASIC?ASIC?(?FPGA?ASIC?ASIC?/?ASIC?(FPGA?FPGA?(FPGA?!#?ASIC?jk?6?vw.?.?89?=?=jk?!?#$?%?
3、AB?F?0 3T=tCO+tDELAY+tSU$%&?T()*+,-./0$%&?T(?1234$5()*+6789:;?$%AB f=1/TDQDQCDCLKINPUTtCOtDELAYtSUOUT!/#?$(Setup/Hold time)?V0Setup time3tSU?R?z?PY“?V&?V0Hold time3tH?R?z?PY“?V&tSUtHDataClock!/#?$(Setup/Hold Time)Y#$?/?V?tSU-34$5?Setup time?(tH-EF$5?Hold time?tCO$%GHI$5?Clock-to-Output time?tMET 34$
4、5?Setting time?:;G;?$5(J+K.LMN?AN42-Metastability in Altera Devices?%&(Timing Constraints)?.?89.?0P&R389?0STA389?P?/?.?J.?F?EDA89?P?8?&?89?P?/?4#$?%&?89?P?/?#$?%&?89?P?/?#$?%&?(Timing Closure)?CD?89.?89?P?jk?D?#$?&?#$?&/?IC?89Y?a?.?.?!/?&)*+,(Critical Path)?C?AB?4?F?45&#?T45?M?$P%&?45&?4?T45&CD(?=?)
5、PT45&MT45jk?!?!?&MAB?Pipeline.Retiming*?&?+,(Timing Paths)+?45O HPQRG)*+S)*+G)*+T)*+GHIQRU HPQRGHIQR?-.!(Clock-to-Setup Path)Clock-to-Setup PathtSU-$%G34$V?-.!(Clock-to-Setup Path)Clock-to-Setup Path?-.!(Clock-to-Setup Path)Rising to Falling Edge?-.!(Clock-to-Setup Path)Falling to Rising Edge?-./0(C
6、lock-to-Pad Path)Clock-to-Pad Path?-./0(Clock-to-Pad Path)Clock-to-Pad PathWXYZ?_1&2?-30(Paths Ending at Clock Pin of Filp-Flops)Ending at Clock Pin of F-F/04?!.?-(Setup to Clock at the Pad)Setup to Clock at the Pad?-/0.56/0(Clock Pad to Output Pad)Clock Pad to Output Pad?R,?,/0./0(Pad to Pad)Pad to
7、 PadtPD G$V/0./0(Pad to Pad)Pad to Pad Path/0.!(Pad to Setup)Pad to Setup789:Clock-to-Setup PathClock-to-Setup Path$abcdef789:Clock-to-Pad PathClock-to-Pad Path$abcdef789:;?(Clock Skew)Clock Skew?R-?./01?%?R2A?(Off-Chip Delay)Off-Chip Delay?6$PW3?Rtu?PW3?R?45?F&67?8?9?F?E)&?BCDERetiming?BCDEPipelini
8、ng?FGTiming AnalyzerTiming AnalyzerAlteraMAX+plus II:?89?jk+?45?F?0Delay Matrix3?/?V?0Setup/Hold3*?AB?0Registered Performance3?FGTiming AnalyzerTiming Analyzer?VCC9clkINPUT4DDFFCLRNQPRN5DDFFCLRNQPRNVCC7aINPUTVCC8inputINPUT6AND210outputOUTPUT+KqrsEPM7256AEQC208-10?FGTiming AnalyzerTiming Analyzer Del
9、ay Matrix45?F?g;?g/?,DFF?z?.?R.?R?%?.?V?FGTiming AnalyzerTiming Analyzer Registered PerformanceAB?AB?)PA?F.?R?.?R?&BCD?E6)5F?.?V?&?FGTiming AnalyzerTiming Analyzer Registered Performance10.5 ns?tuij?$V?q(T=tCO+tDELAY+tSUvMAX7000A/E datasheet(EPM7256AEQC208-10+K(tCOwxyz|?tRD(?B1.6ns0tSUwxyz|?tSU(?B2.
10、9ns0w?(?+4:Q?+5:D?5?cdBN?cd(?tDELAY|?4:Q?5:D?5?$V(vDelay Matrixab?(tDELAYB6.0ns=T=tCO+tDELAY+tSU=1.6ns+6.0ns+2.9ns=10.5nsH?PrimeTime!#$%&(#)*+,-?.#/0123?45?FGPrimeTimePrimeTime?Synopsys?89?G?H?IJKL&PrimeTime?zMASIC?sign-off?N89?hiEDA89?IC?O?&FPGA?SPrimeTime?5?&?Arrival Time!PQBC?Eh?4?f?RM?V?N?f?45?V
11、SD?T?45D?UV?VF?H?#?Required Arrival Time!?RAT PQ?%?4?f?WPn?V$%Slack!PQ?4?f?WPn?%?VBC?VV?X&Slack?YPQT?Z?Z?IJKL?MN11QAQBQCQDRCOALDNBCDENTENPCLKCLRN74162COUNTERMAX+plus II?Timing Analyzer?74162?!8?&0?74162?)5?4?jk?3/?+EPF6024AQC240-3?MN2MAX+plus II?Timing Analyzer?TMU&?)5?R?8?#$?%&/?+EPF6024AQC240-3?FG
12、PrimeTimePrimeTime(Xilinx)*+,?FGPrimeTimePrimeTime(Altera)*+,B?F?(6?+K?Altera?Xilinx?.?FPrimeTime=set search_path.$QUARTUS_ROOTDIR/eda/synopsys/primetime/libset link_path*alt_vtl.db apex20ke_asynch_mem_lib.db apex20ke_lvds_receiver_lib.dbapex20ke_cam_lib.db apex20ke_lvds_transmitter_lib.db apex20ke_
13、io_lib.db apex20ke_pll_lib.dbapex20ke_lcell_lib.db apex20ke_pterm_lib.dbread_verilog$QUARTUS_ROOTDIR/eda/synopsys/primetime/lib/apex20ke_camslice_pt.v read_verilog$QUARTUS_ROOTDIR/eda/synopsys/primetime/lib/apex20ke_ramslice_pt.v read_verilog snug_pt.vocurrent_design snuglink_design snugread_sdf snu
14、g_v.sdo?FGPrimeTimePrimeTime(Altera)*+,Script?create_clock“CLK”-period 4 waveform 0 2check_timingreport_analysis_coveragereport_timing?FGPrimeTimePrimeTime(Altera)*+,Script?FGPrimeTimePrimeTime?(Xilinx?-.FPGA?/01TIGset_false_path45MAXDELAYset_max_delay?FOFFSET OUTset_output_delay?FOFFSET INset_input
15、_delay?FPERIODcreate_clock?R?UCF?SDC?SDC Synopsys Design ConstraintsUCF Xilinx User Constraints File?FGPrimeTime23?45clock delay 1+max data path-clock delay 2+tsu 6 clock period?FGPrimeTime23?45?$%?Global Clock?k?(Clock delay 6?B!0ns?Max data path!?+?tCO$5?+?5?cd$V?tsu!)*+?34$5Clock Delay 1=0nsClock
16、 Delay 2=0nsMax Data Path=tco of source reg+path between reg=1.449ns+.258ns=1.707nsWith 4ns clock period,the slack is 4ns-1.707ns=2.293ns?FGPrimeTime23?45?FGPrimeTime23?45?PrimeTimeab?METs1234$5VIOLATEDs?1278?45?FGPrimeTimeclock delay 1+minimum data delay clock delay 2 th 9 078?45?FGPrimeTime?$%?Glo
17、bal Clock?k?(Clock delay 6?B!0ns?Min data path!?+?tCO$5?+?5?cd$V?th!)*+?34$5Clock Delay 1=0nsClock Delay 2=0nsMinimum Data Path=tco of source reg+path between reg=1.449ns+.258ns=1.707nsIntrinsic hold time=1.284nsSlack is 1.707ns-1.284ns=0.493ns?FGPrimeTime78?45?FGPrimeTime78?45?PrimeTimeab?METs1234$5VIOLATEDs?12
