1、Rev.0,03/09,WK Page 1 of 14MT-101去耦技术图1：AD8099高性能运算放大器的电源抑制与频率的关系指南何谓正确去耦？有何必要性？如果电源引脚上存在纹波和/或噪声，大多数IC都会有某种类型的性能下降。数字IC的噪声裕量会降低，时钟抖动则可能增加。对于高性能数字IC，例如微处理器和FPGA，电源额定容差(例如5%)包含直流误差、纹波和噪声之和。只要电压保持在容差内，数字器件便符合规范。说明模拟IC对电源变化灵敏度的传统参数是电源抑制比(PSRR)。对于放大器，PSRR是输出电压变化与电源电压变化之比，用比率(PSRR)或dB(PSR)表示。PSRR可折合到输出端(R
2、TO)或输入端(RTI)。RTI值等于RTO值除以放大器增益。图1显示典型高性能放大器(AD8099)PSR随频率、以大约6 dB/8倍频程(20 dB/10倍频程)下降的情况。图中显示了采用正负电源两种情况下的曲线图。尽管PSR在直流下是90 dB，但较高频率下会迅速降低，此时电源线路上有越来越多的无用能量会直接耦合至输出。因此必须一开始就要防止此高频能量进入芯片。一般通过组合电解电容(用于低频去耦)、陶瓷电容(用于高频去耦)来完成，也有可能使用铁氧体磁珠。数据转换器以及其他模拟和混合信号电路的电源抑制可能在数据手册中都有相关规定。不过，在数据手册的应用部分，经常会针对几乎所有的线性和混合信
3、号IC推荐电源去耦电路。用户应始终遵循这些建议，以确保器件正常工作。Page 2 of 14 MT-101图2：何谓正确去耦？A large electrolytic capacitor(typically 10 F 100 F)no more than 2 in.away from the chip.The purpose of this capacitor is to be a reservoir of charge to supply the instantaneous charge requirements of the circuits locally so the charge n
4、eed not come through the inductance of the power trace.A smaller cap(typ.0.01 F 0.1 F)as physically close to the power pins of the chip as is possible.The purpose of this capacitor is to short the high frequency noise away from the chip.All decoupling capacitors should connect to a large area low im
5、pedance ground plane through a via or short trace to minimize inductance.Optionally a small ferrite bead in series with the supply pin.Localizes the noise in the system.Keeps external high frequency noise from the IC.Keeps internally generated noise from propagating to the rest of the system.低频噪声需要较
6、大的电解电容，用作瞬态电流的电荷库。将低电感表面贴装陶瓷电容直接连接到IC电源引脚，便可最大程度地抑制高频电源噪声。所有去耦电容必须直接连接到低电感接地层才有效。此连接需要短走线或过孔，以便将额外串联电感降至最低。铁氧体磁珠(以镍、锌、锰的氧化物或其他化合物制造的绝缘陶瓷)也可用于在电源滤波器中去耦。铁氧体在低频下(10kNEGLECTS RS0.10.01ESRESLCFILTERGAINRSlogESLC112fR使用铁氧体磁珠代替电感可以减少谐振问题，因为铁氧体磁珠在100 kHz以上表现为阻性，所以会降低电路的有效Q值。典型铁氧体磁珠阻抗如图8所示。简单LRC去耦网络的响应可以使用基于
7、SPICE的程序轻松仿真，例如National Instruments Multisim，ADI公司版。典型电路模型如图9所示，仿真响应如图10所示。Page 9 of 14 MT-101图10：使用NI Multisim Analog Devices版仿真LC网络增益图11：去耦对AD8000运算放大器性能的影响VLOADRLOAD10kESL4nHESR50mC100FL100HRS50m1.6kHzESLLESLL20 log=88dB2 f LESRFILTERGAINProper decouplingNo decoupling不良去耦技术对性能的影响本节考察不良去耦技术对两种基础元件
8、：运算放大器和ADC的影响。图11显示1.5 GHz高速电流反馈运算放大器AD8000的脉冲响应。两种示波器图表均使用评估板获得。左侧走线显示正确去耦的响应，右侧走线显示同一电路板上去除去耦电容后的相同响应。两种情况中，输出负载均为100。Page 10 of 14 MT-101图12：AD8000电源抑制比(PSRR)图13：AD8000正PSRR测试设置图12显示AD8000的PSRR，它与频率成函数关系。请注意，较高频率下PSRR下降至相对较低值。这意味着电源线路上的信号很容易传播至输出电路。图13显示用于测量AD8000 PSRR的电路。现在考察正确及错误去耦对14位、105/125M
9、SPS高性能数据转换器ADC AD9445的影响。虽然转换器通常无PSRR规格，但正确去耦仍非常重要。图14显示正确设计电路的FFT输出。这种情况下，对AD9445使用评估板。注意频谱较为干净。Page 11 of 14 MT-101图14：正确去耦时AD9445评估板的FFT坐标图图15：AD9445引脚排列图AD9445的引脚排列如图15所示。请注意，电源和接地引脚有多个。这是为了降低电源阻抗(并联引脚)。模拟电源引脚有33个。18个引脚连接到AVDD1(电压为+3.3 V 5%)，15个引脚连接到AVDD2(电压为+5 V 5%)。DVDD(电压为+5 V 5%)引脚有4个。在本实验中所
10、用的评估板上，每个引脚具有陶瓷去耦电容。此外还有数个10 F电解电容。Page 12 of 14 MT-101图16：从模拟电源去除电容后AD9445评估板的FFT坐标图图16显示了从模拟电源去除去耦电容后的频谱。请注意，高频杂散信号增加了，还出现了一些交调产物(低频成分)。信号SNR已显著降低。本图与上图的唯一差异是去除了去耦电容。同样使用AD9445评估板进行测量。图17显示从数字电源去除去耦电容的结果。注意杂散同样增加了。另外应注意杂散的频率分布。这些杂散不仅出现在高频下，而且跨越整个频谱。本实验使用转换器的LVDS版本进行。可以想象，CMOS版本会更糟糕，因为LVDS的噪声低于饱和CM
11、OS逻辑。Page 13 of 14 MT-101图17：从数字电源去除电容后AD9445评估板的SNR图参考文献：1.Henry W.Ott,Noise Reduction Techniques in Electronic Systems,2nd Edition,John Wiley,Inc.,1988,ISBN:0-471-85068-3.2.Paul Brokaw,An IC Amplifier Users Guide to Decoupling,Grounding and Making Things Go Right for a Change,Analog Devices,AN-202
12、.3.Paul Brokaw,Analog Signal-Handling for High Speed and Accuracy,Analog Devices,AN-342.4.Jerald Graeme and Bonnie Baker,Design Equations Help Optimize Supply Bypassing for Op Amps,Electronic Design,Special Analog Issue,June 24,1996,p.9.5.Jerald Graeme and Bonnie Baker,Fast Op Amps Demand More Than
13、a Single-Capacitor Bypass,Electronic Design,Special Analog Issue,November 18,1996,p.9.6.Jeffrey S.Pattavina,Bypassing PC Boards:Thumb Your Nose at Rules of Thumb,EDN,Oct.22,1998,p.149.7.Howard W.Johnson and Martin Graham,High-Speed Digital Design,PTR Prentice Hall,1993,ISBN-10:0133957241,ISBN-13:978
14、-0133957242.8.Ralph Morrison,Solving Interference Problems in Electronics,John Wiley,1995,ISBN-10:0471127965,ISBN-13:978-0471127963 9.C.D.Motchenbacher and J.A.Connelly,Low Noise Electronic System Design,John Wiley,1993,ISBN-10:0471577421,ISBN-13:978-0471577423.10.Mark Montrose,EMC and the Printed C
15、ircuit Board,Wiley-IEEE Press,1999,ISBN-10:078034703X,ISBN-13:978-0780347038.Page 14 of 14 MT-10111.Bonnie Baker,A Bakers Dozen:Real Analog Solutions for Digital Designers,Elsevier/Newnes,2005,ISBN-10:0750678194,ISBN-13:978-0750678193.12.Jerald Graeme,Optimizing Op Amp Performance,McGraw Hill,1996,I
16、SBN-10:0070245223,ISBN-13:978-0070245228.13.Tamara Schmitz and Mike Wong,Choosing and Using Bypass Capacitors(Part 1 of 3),Planet Analog,June 19,2007.14.Tamara Schmitz and Mike Wong,Choosing and Using Bypass Capacitors(Part 2 of 3),Planet Analog,June 21,2007.15.Tamara Schmitz and Mike Wong,Choosing
17、and Using Bypass Capacitors(Part 2 of 3),Planet Analog,June 27,2007.16.Yun Chase,Introduction to Choosing MLC Capacitors for Bypass/Decoupling Applications,AVX Corporation,Myrtle Beach,SC.17.Panasonic SP-Capacitor Technical Guide,Panasonic,Inc.18.National Instruments Multisim,Analog Devices Edition1
18、9.Hank Zumbahlen,Basic Linear Design,Analog Devices,2006,ISBN:0-915550-28-1.Also available asLinear Circuit Design Handbook,Elsevier-Newnes,2008,ISBN-10:0750687037,ISBN-13:978-0750687034.Chapter 1220.Walter G.Jung,Op Amp Applications,Analog Devices,2002,ISBN 0-916550-26-5,Chapter 7.Also available as
19、 Op Amp Applications Handbook,Elsevier/Newnes,2005,ISBN 0-7506-7844-5.Chapter 7.21.Walt Kester,High Speed System Applications,Analog Devices,2006,ISBN-10:1-56619-909-3,ISBN-13:978-1-56619-909-4,Part 4.Copyright 2009,Analog Devices,Inc.All rights reserved.Analog Devices assumes no responsibility for
20、customer product design or the use or application of customers products or for any infringements of patents or rights of others which may result from Analog Devices assistance.All trademarks and logos are property of their respective holders.Information furnished by Analog Devices applications and development tools engineers is believed to be accurate and reliable,however no responsibility is assumed by Analog Devices regarding technical accuracy and topicality of the content provided in Analog Devices Tutorials.
