1、8.2 .3程序设计与仿真例1:FPGA驱动LED静态显示-文件名:decoder.vhd-功能:译码输出模块,LED为共阳接法-最后修改日期:2004.3.24library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;entity decoder isPort (seg:in std_logic_vector(3 downto 0 ); -四位二进制码输入q3:out std_logic_vector(6 downto 0) ); -输出LED七段
2、码end decoder;architecture Behavioral of decoder isbeginprocess(seg)begincase seg iswhen 0000 = q3 q3 q3 q3 q3 q3 q3 q3 q3 q3 q3=1111111;end case;end process;end Behavioral;例2:FPGA驱动LED动态显示(4位)-文件名:dynamic.vhd。-功能:动态扫描模块,位选信号高电平有效。-最后修改日期:2004.3.24。library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.ST
3、D_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;entity dynamic is Port ( clk : in std_logic; reset: in std_logic; din1 : in std_logic_vector(6 downto 0); -译码后的数据信号1(4位2进制数据通过例1中的decoder模块译码得到din1,din2,din3,din4) din2 : in std_logic_vector(6 downto 0); -译码后的数据信号2 din3 : in std_logic_vector(6 downto
4、 0); -译码后的数据信号3 din4 : in std_logic_vector(6 downto 0); -译码后的数据信号4 shift: out std_logic_vector(3 downto 0); -位选信号 bus4 : out std_logic_vector(6 downto 0); -数据信号end dynamic;architecture Behavioral of dynamic is signal scan_clk:std_logic_vector(1 downto 0);beginprocess(clk,scan_clk,reset) -分频进程variable scan:std_logic_vector(17 downto 0);beginif reset=1 thenscan:=000000000000000000;scan_clk=00;elsif clkevent and clk=1thenscan:=scan+1;end if;scan_clk bus4=din1; shift bus4=din2; shift bus4=din3; shift bus4=din4; shift bus4=0000000;shift=0000;end case;end process; end Behavioral;