1、 IEC 62530 Edition 2.0 2011-05 INTERNATIONAL STANDARD SystemVerilog Unified Hardware Design,Specification,and Verification Language IEC 62530:2011(E)IEEE Std 1800-2009 IEEE Std 1800 colourinsideCopyrighted material licensed to BR Demo by Thomson Reuters(Scientific),Inc.,downloaded on Nov-28-2014 by
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10、pyrighted material licensed to BR Demo by Thomson Reuters(Scientific),Inc.,downloaded on Nov-28-2014 by James Madison.No further reproduction or distribution is permitted.Uncontrolled when printed.IEC 62530Edition 2.0 2011-05INTERNATIONAL STANDARD SystemVerilog Unified Hardware Design,Specification,
11、and Verification Language INTERNATIONAL ELECTROTECHNICAL COMMISSION XXICS 25.040 PRICE CODEISBN 978-2-88912-450-3 IEEE Std 1800 colourinsideCopyrighted material licensed to BR Demo by Thomson Reuters(Scientific),Inc.,downloaded on Nov-28-2014 by James Madison.No further reproduction or distribution
12、is permitted.Uncontrolled when printed.Copyrighted material licensed to BR Demo by Thomson Reuters(Scientific),Inc.,downloaded on Nov-28-2014 by James Madison.No further reproduction or distribution is permitted.Uncontrolled when printed.-i-IEC 62530:2011(E)IEEE Std 1800-2009Published by IEC under l
13、icense from IEEE.2009 IEEE.All rights reserved.Contents Part One:Design and Verification Constructs1.Overview.21.1Scope.21.2Purpose.21.3Merger of IEEE Std 1364-2005 and IEEE Std 1800-2005.31.4Special terms.31.5Conventions used in this standard.31.6Syntactic description.41.7Use of color in this stand
14、ard.51.8Contents of this standard.51.9Deprecated clauses.81.10 Examples.81.11 Prerequisites.82.Normative references.93.Design and verification building blocks.113.1General.113.2Design elements.113.3Modules.113.4Programs.123.5Interfaces.133.6Checkers.143.7Primitives.143.8Subroutines.143.9Packages.143
15、.10 Configurations.153.11 Overview of hierarchy.153.12 Compilation and elaboration.163.13 Name spaces.183.14 Simulation time units and precision.194.Scheduling semantics.234.1General.234.2Execution of a hardware model and its verification environment.234.3Event simulation.234.4The stratified event s
16、cheduler.244.5The SystemVerilog simulation reference algorithm.294.6Determinism.294.7Nondeterminism.304.8Race conditions.304.9Scheduling implication of assignments.304.10 The PLI callback control points.325.Lexical conventions.335.1General.335.2Lexical tokens.335.3White space.335.4Comments.335.5Operators.335.6Identifiers,keywords,and system names.345.7Numbers.355.8Time literals.40Copyrighted material licensed to BR Demo by Thomson Reuters(Scientific),Inc.,downloaded on Nov-28-2014 by James