1、STP1382 Gate Dielectric Integrity:Material,Process,and Tool Qualification Dinesh C.Gupta and George A.Brown,editors ASTM Stock Number:STP1382 100 Barr Harbor Drive West Conshohocken,PA 19428-2959 Library of Congress Cataloging-in-Publication Data Gate dielectric integrity:material,process,and tool q
2、ualification/Dinesh C.Gupta and George A.Brown,Editors.(STP;1382)ASTM Stock Number:STP1382.Includes bibliographical references and index.ISBN 0-8031-2615-8 1.Semiconducto r wafers-Reliability.2.Integrated circuits-Wafer-scale integration-Reliability.3.Gate array circuits-Materials.4.Silicon oxide fi
3、lms-Testing.5.Dielectrics-Testing.I.Gupta,D.C.(Dinesh C.)I1.Brown,George A.1937-TK7871.85.G32 2000 621.38152-dc21 99-086920 Copyright?9 2000 AMERICAN SOCIETY FOR TESTING AND MATERIALS,West Conshohocken,PA.All rights reserved.This material may not be reproduced or copied,in whole or in part,in any pr
4、inted,mechanical,electronic,film,or other distribution and storage media,without the written consent of the publisher.Photocopy Rights Authorization to photocopy items for internal,personal,or educational classroom use,or the internal,personal,or educational classroom use of specific clients,is gran
5、ted by the American Society for Testing and Materials(ASTM)provided that the appropdate fee is paid to the Copyright Clearance Center,222 Rosewood Drive,Danvers,MA 01923;Tel:508-750-8400;online:http:/ Review Policy Each paper published in this volume was evaluated by two peer reviewers and the edito
6、r.The authors addressed all of the reviewers comments to the satisfaction of both the technical editor(s)and the ASTM Committee on Publications.The quality of the papers in this publication reflects not only the obvious efforts of the authors and the technical editor(s),but also the work of the peer
7、 reviewers.In keeping with long standing publi-cation practices,ASTM maintains the anomymity of the peer reviewers.The ASTM Committee on Publications acknowledges with appreciation their dedication and contribution of time and effort on behalf of ASTM.Printed in Mayfield,PA January 2000 Foreword The
8、 Conference on Gate Dielectric Integrity was held on January 25,1999 in San Jose,California.ASTM Committee F-1 on Electronics sponsored the conference.The conference co-chairmen were Dinesh Gupta,of Mitsubishi Silicon America,and George Brown of Texas Instruments(currently as-signed to SEMATECH).The
9、 success of the conference is the result of both the hard work of many people in the industry who participated as coordinators,and the support of the Officers of Committee F-1.George Brown and Dinesh Gupta presided at the technical sessions and Howard Huff of SEMATECH joined Dinesh Gupta and George
10、Brown in moderating the Panel discussions.We are also thankful to all the presenters at the technical sessions who also joined as panel mem-bers.Many scientists from all over the world reviewed the manuscripts published in this book.Without their support,this publication would not have been possible
11、.And finally,we acknowledge the hard work and efforts of the staff at ASTM in bringing the book to print.Contents OverviewDINESH c.GUPTA AND GEORGE A.BROWN CONCEPTS Gate Oxide Reliability Assessment and Some Connections to Oxide Integrity D.J.DUMIN THIN GATE DIELECTRICS Ultra-Thin Film Dielectrics R
12、eliability Charaeterization-J.s.SUEBLE Voltage Step Stress for 10 nm Oxides-A.STRONG Localized Charging Damage in Thin Oxides-G.BERSUKER AND J.WERrdNG CHARACTERIZATION AND APPLICATIONS Characterization of Gate Dielectrics With Mercury Gate MOS Current-Voltage Measurements-.A.GRUBER AND R.J.HILLARD C
13、OCOS(Corona Oxide Characterization of Semiconductor)Metrology:Physical Prindpal and Applieations-M.WILSON AND J.LAGOWSKi,A.SAVTCHOUK,L.JASTRZEBSKI,AND J.DAMICO.Application of Quantox Measurements to Identify Phosphorus Contamination in Silicon Wafers-M.A.DEXTER,K.M.HASSLINGER,J.R.FRITZ,AND C.A.ULLO
14、Applications of Gate Oxide Integrity Measurements in Silicon Wafer ManufaeturingwM.R.SEACRIST Silicon Substrata Related Gate Oxide Integrity at Different Oxide Thieknesses E.D.GRANN,A.HUBER,J.GRABMEIER,R.HOLZL,AND R.WAHLICH Single Wafer Gate Dielectric Technologies for Sub-0.18 wm Applieations-.MINE
15、R,G.XING,Y.YOKOTA,A.JAGGI,E.SANCHEZ,C.CHEN,AND D.LOPEZ High Resolution Gate Oxide Integrity(GOI)Measurement in Near-Perfect Silieon-u MURAKAM1,T,YAMAZAKI,W.ITOU,AND T.SHINGYOUJ Qualification of Epi Layers and Interface Properties by an Improved I-PCD Techque-T.PAVELKA ix 27 41 47 65 74 91 102 112 12
16、2 132 145 STANDARDIZATION AND ROUND ROBINS Appendix lmlntefim Reports of Two Inter-Laboratory Round Robins on Gate Oxide Integrity,One Conducted by ASTM Committee F-1 and JEDEC Committee,and the Other Conducted by JEIDA Committee and SEMI,Japan 157 PANEL DISCUSSIONS Appendix 2.-Pand Discussions-A Synopsis 167 A Note of Appreciation The quality of the papers that appear in this publication reflects not only the obvious efforts of the authors,but also the unheralded,though essential,work of the re
