1、 INTERNATIONAL STANDARD IEC62142 First edition2005-06 IEEE 1364.1Verilog register transfer level synthesis Reference number IEC 62142(E):2005 IEEE Std.1364.1(E):2002 LICENSED TO MECON Limited.-RANCHI/BANGALOREFOR INTERNAL USE AT THIS LOCATION ONLY,SUPPLIED BY BOOK SUPPLY BUREAU.Publication numbering
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8、ON Limited.-RANCHI/BANGALOREFOR INTERNAL USE AT THIS LOCATION ONLY,SUPPLIED BY BOOK SUPPLY BUREAU.Verilog register transfer level synthesis INTERNATIONAL STANDARD IEC62142 First edition2005-06 IEEE 1364.1Commission Electrotechnique InternationaleInternational Electrotechnical Commission IEEE 2005 Co
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10、icrofilm,without permission in writing from the publisher.International Electrotechnical Commission,3,rue de Varemb,PO Box 131,CH-1211 Geneva 20,SwitzerlandTelephone:+41 22 919 02 11 Telefax:+41 22 919 03 00 E-mail:inmailiec.ch Web:www.iec.ch The Institute of Electrical and Electronics Engineers,Inc
11、,3 Park Avenue,New York,NY 10016-5997,USATelephone:+1 732 562 3800 Telefax:+1 732 562 1571 E-mail:stds-infoieee.org Web:www.standards.ieee.org LICENSED TO MECON Limited.-RANCHI/BANGALOREFOR INTERNAL USE AT THIS LOCATION ONLY,SUPPLIED BY BOOK SUPPLY BUREAU.1.Overview.81.1Scope.81.2Compliance to this
12、standard.81.3Terminology.91.4Conventions.91.5Contents of this standard.91.6Examples.102.References.103.Definitions.104.Verification methodology.114.1Comb inational logic verification.124.2Sequential logic verification.125.Modeling hardware elements.135.1Modeling comb inational logic.135.2Modeling ed
13、ge-sensitive sequential logic.145.3Modeling level-sensitive storage devices.175.4Modeling three-state drivers.185.5Support for values x and z.205.6Modeling read-only memories(ROM).205.7Modeling random access memories(RAM).226.Pragmas.236.1Sy nthesis attrib utes.236.2Compiler directives and implicit-
14、sy nthesis defined macros.346.3Deprecated features.357.Sy ntax.367.1Lexical conventions.367.2Data ty pes.417.3Expressions.467.4Assignments.487.5Gate and switch level modeling.497.6User-defined primitives(UDPs).527.7Behavioral modeling.537.8Tasks and functions.597.9Disab ling of named b locks and tas
15、ks.627.10 Hierarchical structures.627.11 Configuring the contents of a design.687.12 Specify b locks.707.13 Timing checks.707.14 Backannotation using the standard delay format.707.15 Sy stem tasks and functions.70IEC 62142:2005(E)IEEE 1364.1-2002(E)2 Published by IEC under licence from IEEE.2005 IEE
16、E.All rights reserved.CONTENTSFOREWORD.4 IEEE Introduction.7LICENSED TO MECON Limited.-RANCHI/BANGALOREFOR INTERNAL USE AT THIS LOCATION ONLY,SUPPLIED BY BOOK SUPPLY BUREAU.7.16 Value change dump(VCD)files.707.17 Compiler directives.707.18 PLI.71Annex A(informative)Sy ntax summary.72A.1Source text.72A.2Declarations.74A.3Primitive instances.79A.4Module and generated instantiation.81A.5UDP declaration and instantiation.82A.6Behavioral statements.83A.7Specify section.87A.8Expressions.92A.9General.9
