1、 IEC/TS 62215-2Edition 1.0 2007-09TECHNICAL SPECIFICATION Integrated circuits Measurement of impulse immunity Part 2:Synchronous transient injection method IEC/TS 62215-2:2007(E)LICENSED TO MECON Limited.-RANCHI/BANGALOREFOR INTERNAL USE AT THIS LOCATION ONLY,SUPPLIED BY BOOK SUPPLY BUREAU.THIS PUBL
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9、 LICENSED TO MECON Limited.-RANCHI/BANGALOREFOR INTERNAL USE AT THIS LOCATION ONLY,SUPPLIED BY BOOK SUPPLY BUREAU.IEC/TS 62215-2Edition 1.0 2007-09TECHNICAL SPECIFICATION Integrated circuits Measurement of impulse immunity Part 2:Synchronous transient injection method INTERNATIONAL ELECTROTECHNICAL
10、COMMISSION UICS 31.200 PRICE CODEISBN 2-8318-9305-4LICENSED TO MECON Limited.-RANCHI/BANGALOREFOR INTERNAL USE AT THIS LOCATION ONLY,SUPPLIED BY BOOK SUPPLY BUREAU.2 TS 62215-2 IEC:2007(E)CONTENTS FOREWORD.4 INTRODUCTION.6 1 Scope.7 2 Normative references.7 3 Terms and definitions.7 4 General.8 4.1
11、Introduction.8 4.2 Measurement philosophy.8 4.3 Set-up concept.9 4.4 Response signal.9 4.5 Coupling networks.10 4.5.1 General.10 4.5.2 Design of coupling networks.10 4.5.3 Coupling network for the ground/Vss pin(s).10 4.5.4 Coupling network for the supply/Vdd pin(s).11 4.5.5 Coupling network for the
12、 I/O pin(s).13 4.5.6 Coupling network for the reference pins.13 4.5.7 Coupling network verification.14 4.6 Test circuit board.14 4.6.1 General.14 4.6.2 IC pin loading/termination.14 4.6.3 Power supply requirements.15 4.7 IC specific considerations.15 4.7.1 IC supply voltage.15 4.7.2 IC decoupling.15
13、 4.7.3 Activity of IC.15 4.7.4 Guidelines for IC stimulation.15 4.7.5 IC monitoring.15 4.7.6 IC stability over time.15 5 Test conditions.16 5.1 Default test conditions.16 5.1.1 General.16 5.1.2 Ambient conditions.16 5.1.3 Ambient temperature.16 5.2 Impulse immunity of the test set-up.16 6 Test set-u
14、p.16 6.1 General.16 6.2 Test equipment.17 6.3 Set-up explanation.17 6.4 Explanation of signal relations.18 6.5 Calculation of time step and number of measurements to be conducted.18 6.6 Test procedure.19 6.7 Monitoring check.19 6.8 System verification.19 LICENSED TO MECON Limited.-RANCHI/BANGALOREFO
15、R INTERNAL USE AT THIS LOCATION ONLY,SUPPLIED BY BOOK SUPPLY BUREAU.TS 62215-2 IEC:2007(E)3 7 Test report.20 7.1 General.20 7.2 Immunity limits or levels.20 7.3 Performance classes.20 7.4 Interpretation and comparison of results.20 Annex A(informative)Flow chart of the software used in a microcontro
16、ller.21 Annex B(informative)Flow chart for the set-up control S/W(bus control program).22 Annex C(informative)Test board requirements.23 Bibliography.27 Figure 1 Synchronous transient injection immunity methodology waveforms.9 Figure 2 Test set-up diagram for synchronous transient injection immunity testing.10 Figure 3 Circuit diagram of the coupling network for ground/Vss pin(s)of an IC.11 Figure 4 Method to impose synchronous transient injection into ground/Vss pin(s).11 Figure 5 Circuit diagr
