1、Designation:F 1153 92(Reapproved 1997)Standard Test Method forCharacterization of Metal-Oxide-Silicon(MOS)Structures byCapacitance-Voltage Measurements1This standard is issued under the fixed designation F 1153;the number immediately following the designation indicates the year oforiginal adoption o
2、r,in the case of revision,the year of last revision.A number in parentheses indicates the year of last reapproval.Asuperscript epsilon(e)indicates an editorial change since the last revision or reapproval.1.Scope1.1 This test method covers procedures for measurement ofmetal-oxide-silicon(MOS)structu
3、res for flatband capacitance,flatband voltage,average carrier concentration within a deple-tion length of the semiconductor-oxide interface,displacementof flatband voltage after application of voltage stress atelevated temperatures,mobile ionic charge contamination,andtotal fixed charge density.Also
4、 covered is a procedure fordetecting the presence of P-N junctions in the subsurfaceregion of bulk or epitaxial silicon.1.2 The procedure is applicable to n-type and p-type bulksilicon with carrier concentration from 5 3 1014to 5 3 1016carriers per cm3,inclusive,and N/N+and P/P+epitaxialsilicon with
5、 the same range of carrier concentration.1.3 The procedure is applicable for test specimens withoxide thicknesses of 50 to 300 nm.1.4 The procedure can give an indication of the level ofdefects within the MOS structure.These defects includeinterface trapped charge,fixed oxide charge,trapped oxidecha
6、rge,and permanent inversion layers.1.5 The precision of the procedure can be affected byinhomogeneities in the oxide or in the semiconductor parallelto the semiconductor-oxide interface.1.6 The procedure is applicable for measurement of mobileionic charge concentrations of 1 3 1010cm2or greater.Alte
7、rnative techniques,such as the triangular voltage sweepmethod2(1),may be required where mobile ionic chargeconcentrations less than 1 3 1010cm2must be measured.1.7 The procedure is applicable for measurement of totalfixed charge density of 5 3 1010cm2or greater.Alternativetechniques,such as the cond
8、uctance method(2),may berequired where the interface trapped-charge density componentof total fixed charge of less than 5 3 1010cm2must bemeasured.1.8 This standard does not purport to address all of thesafety concerns,if any,associated with its use.It is theresponsibility of the user of this standa
9、rd to establish appro-priate safety and health practices and determine the applica-bility of regulatory limitations prior to use.2.Referenced Documents2.1 ASTM Standards:F 388 Method for Measurement of Oxide Thickness onSilicon Wafers and Metallization Thickness by MultipleBeam Interference(Tolansky
10、 Method)3F 576 Test Method for Measurement of Insulator Thicknessand Refractive Index on Silicon Substrates by Ellipsom-etry4F 723 Practice for Conversion Between Resistivity andDopant Density for Boron-Doped and Phosphorus-DopedSilicon43.Terminology3.1 Definitions of Terms Specific to This Standard
11、:3.2 accumulation conditionthe region of the C-V curvefor which a 5 V increment toward a more negative voltage forp-type material(Fig.1),or toward a more positive voltage forn-type material(Fig.2),results in less than a 1%change in themaximum capacitance,Cmax.3.3 equilibrium capacitancethat capacita
12、nce reached afteran MOS specimen at a fixed bias is illuminated and thenallowed to stabilize in darkness.3.4 flatband condition,in microelectronicsthe point atwhich an external applied voltage causes there to be no internalpotential difference across an MOS structure.Under practicalconditions,metal-
13、semiconductor work-function differencesand charges in the oxide require the application of an externalvoltage to produce the flatband condition.3.5 flatband voltage,Vfbthe applied voltage necessary toproduce the flatband condition.3.6 flatband capacitance,Cfbthe capacitance of an MOSstructure at the
14、 flatband voltage.3.7 inversion conditionfor the purposes of this testmethod and for measurements on surfaces that do not exhibit apermanent inversion layer,the region of the Capacitance-Voltage,(C-V)curve for which a 5 V increment toward a morepositive voltage for p-type material(Fig.1),or toward a
15、 morenegative voltage for n-type material(Fig.2),results in less than1This test method is under the jurisdiction of ASTM Committee F-1 onElectronics and is the direct responsibility of Subcommittee F01.06 on SiliconMaterials and Process Control.Current edition approved May 15,1992.Published July 199
16、2.Originallypublished as F 1153 88.Last previous edition F 1153 88.2Boldface numbers in parentheses refer to the list of references at the end of thistest method.3Discontinued;see 1992 Annual Book of ASTM Standards,Vol 10.05.4Annual Book of ASTM Standards,Vol 10.05.1AMERICAN SOCIETY FOR TESTING AND MATERIALS100 Barr Harbor Dr.,West Conshohocken,PA 19428Reprinted from the Annual Book of ASTM Standards.Copyright ASTM1%change in the equilibrium minimum capacitance,Cmin.3.8 permanent inversion layer
